New device architecture shrinks logic cells.
Manufacturers of cutting-edge computer processors are undergoing the first major device architecture shift in a decade: the transition from fin field-effect transistors (FinFETs) to nanosheets.

In another decade, another fundamental shift may occur: stacking nanosheets together to form complementary field-effect transistors (CFETs), which could halve the size of some circuits.

But experts say the latter transition is likely to be quite difficult. Meanwhile, the forksheet transistor, somewhere in between, may require less work to keep circuit sizes down.

Julien Ryckaert, vice president of logic technology at the Belgian microelectronics research center (IMEC), says the idea for the forksheet stems from exploring the limits of nanosheet architecture.

A nanosheet's key feature is a horizontal stack of silicon strips surrounded by a current-controlling gate. Although nanosheet production has only recently begun, experts have been searching for its limits for several years. Imec needs to figure out "where nanosheets start to fail," Ryckaert says.

Reicart's team discovered that a certain spacing must be maintained between the N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) transistors that make up complementary metal oxide semiconductor (CMOS) logic to limit the capacitance that degrades device performance and power consumption. This spacing limits the scaling of nanosheet-based logic. "Forksheets are a way to overcome this limitation," Reicart said.

Unlike individual nanosheet devices, forksheets are constructed by placing them in pairs on either side of a dielectric wall. (Not really like a fork.) Naoto Horiguchi, head of CMOS technology at the Belgian Research Center for Microelectronics, says the dielectric wall allows devices to be placed closely together without capacitance issues. He says designers can use the added space to shrink logic cells or use the existing space to make wider transistors for better performance.

"CFETs could be the ultimate CMOS architecture," Horiguchi said, referring to a device that the Belgian Research Center for Microelectronics expects to enter production around 2032. However, he added that CFETs are "very complex to integrate." He says the forksheet will reuse most of the nanosheet production steps, which could make it easier.

However, many hurdles still need to be overcome. From a production perspective, the dielectric wall is a problem. Several types of dielectrics are used in advanced CMOS, and etching involves several steps.

Making the forksheet means etching other components without accidentally damaging the dielectric wall. Horiguchi says the choice of transistor type on either side of the dielectric wall remains an open question. Placing both transistor types on either side of the dielectric wall may offer advantages, rather than placing PMOS on one side and NMOS on the other.